Unlocking the Power of AI in EDA: How Siemens and NVIDIA Are Shaping the Future of Semiconductor Design

At the Design Automation Conference (DAC) 2025, artificial intelligence took center stage. From presentations to research papers, AI was the common thread driving conversations. But one session truly stood out for its depth and real-world application: DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA.

This discussion went beyond hype, delivering practical insights, measurable results, and a clear roadmap for applying AI to solve the most pressing challenges in Electronic Design Automation (EDA) and semiconductor development.

The Rising Role of AI in Semiconductor Design

The semiconductor market is entering a period of unprecedented acceleration. According to Amit Gupta of Siemens EDA, the industry is expected to reach $1 trillion by 2030, with growth doubling to $2 trillion within the following decade. This rapid expansion is fueled by AI-driven workloads that require highly specialized, purpose-built silicon.

But this growth comes with challenges:

• Increasing chip design complexity

• Ever-shorter time-to-market demands

• A shortage of skilled engineering talent

The question is clear: How can semiconductor companies design faster, smarter, and with higher quality? The answer lies in AI built for EDA.

Siemens EDA’s AI System: Built for the Complexity of Chip Design

Amit Gupta, Head of Siemens’ Custom IC division, emphasized that EDA AI is fundamentally different from consumer AI. While general AI handles image recognition and language tasks, EDA AI must manage:

• Technical documentation

• Script generation

• Test bench creation

• Specialized design formats like Verilog and GDSII

To address these needs, Siemens introduced the Siemens EDA AI System—a framework that integrates generative AI and agentic AI across the entire semiconductor design workflow.

This system not only optimizes tool runtimes and improves quality of results but also allows engineers to interact with complex systems using natural language commands. As Gupta describes it, this AI framework acts as the connective tissue linking data, design tools, and human expertise.

NVIDIA’s Role: Supercomputing for EDA AI

Taking the stage next, Dr. John Linford from NVIDIA detailed how their supercomputing infrastructure is co-designed with hardware, software, and networking to accelerate both NVIDIA’s internal chip design and its customers’ projects.

Key enablers for AI in EDA include:

• CUDA-X: Over 450 domain-specific accelerated computing libraries, powering applications from chip lithography to fluid dynamics and thermal analysis.

• NVIDIA NeMo: A Python-based framework for building enterprise-grade AI solutions with built-in guardrails.

• NVIDIA Inference Microservices (NIM): Modular AI building blocks for on-premises or cloud deployment.

Linford also explained how NVIDIA’s AI inference accelerates physical simulation—a major advantage in developing digital twins—reducing verification time while preserving accuracy.

Strategic Collaboration Driving Industry Transformation

The Siemens-NVIDIA collaboration blends domain expertise in semiconductor design with cutting-edge computing infrastructure. Together, they deliver:

• Hardware acceleration for high-compute workloads

• Domain-optimized AI models tailored for EDA

• Deployable AI microservices for seamless integration into engineering pipelines

This partnership showcases AI’s potential to transform the semiconductor industry—not by replacing engineers, but by empowering them to achieve more in less time.

The Future of EDA: AI-Powered, Software-Defined, Silicon-Enabled

The key takeaway from DAC TechTalk 2025 is that AI is becoming a core pillar of modern semiconductor design. Companies that adopt AI as a strategic partner, rather than a peripheral tool, will lead in an era defined by complexity, speed, and innovation.

The Siemens-NVIDIA partnership is a clear example of how AI in EDA can deliver real, measurable results—from improved design quality to reduced time-to-market—setting a new benchmark for the future of chip design.

Source - Semiwiki