S2C Advances RISC-V Ecosystem, Accelerating Innovation at RISC-V Summit China 2025

The RISC-V Summit China 2025 was more than just another industry gathering—it was a showcase of how open-standard architectures are reshaping the semiconductor landscape. Among the standout participants, S2C demonstrated why it has become a key player in accelerating verification and prototyping across the RISC-V ecosystem.

Delivering End-to-End Verification Solutions

Verification remains one of the most critical bottlenecks in chip design, particularly for RISC-V where custom extensions and diverse applications add complexity. S2C has built a comprehensive digital EDA portfolio that spans the entire spectrum of verification, from IP-level validation to system-level deployment. This breadth allows RISC-V developers to shorten design cycles, reduce risk, and move from concept to commercialization with confidence.

Live Demonstrations that Showed Real Progress

At the summit, S2C captured attention by moving beyond slides and presentations to showcase working demonstrations of some of the most ambitious RISC-V designs:

• Xiangshan Processor: Demonstrated running a full graphical Linux interface on S2C’s FPGA prototyping platform.

• Kunminghu Processor: A third-generation 16-core RISC-V design with NoC interconnect, validated on S8-100Q Logic Systems (with 8 VP1902 FPGAs) achieving timing closure at 12 MHz.

• Xuantie R908: A high-efficiency processor for real-time applications, showcased on the S7-19P Logic System to highlight low-latency performance and reliability.

• Andes AX45MPV: A 64-bit RISC-V vector processor IP core, running Linux and large language models efficiently on S2C’s S8-100 Logic System via the Andes Custom Extension (ACE) framework.

These demonstrations underscored not only the maturity of RISC-V designs but also S2C’s critical role in accelerating their development cycles. BOSC, a long-time collaborator on the Xiangshan project, recognized S2C as a “Strategic Contributor” for its impact on advancing open-source processor development.

Breaking Through Verification Bottlenecks

As RISC-V designs scale in complexity, traditional simulation faces inherent limitations: slow execution speeds, limited visibility, and difficulty handling system-level verification.

In response, S2C is championing Transaction-Based Acceleration (TBA), a methodology presented by Senior Engineer Dehao Yang during the summit. TBA decomposes verification into reusable transaction flows, leveraging co-simulation between virtual prototypes and hardware emulation. Combined with S2C’s Genesis Architect and OmniArk/OmniDrive tools, this approach significantly improves verification throughput and observability while maintaining compliance with the RISC-V Verification Interface (RVVI).

By addressing one of the most persistent bottlenecks in the chip design process, TBA enables faster innovation without compromising accuracy or standards.

Commitment to Ecosystem Growth

S2C’s leadership at the RISC-V Summit was not just technical but also collaborative. As VP of Marketing Ying J Chen emphasized, the company views itself not only as a tool provider but also as a partner in innovation. Its deepening partnerships with BOSC, Xuantie, and Andes Technology reflect a strategic vision of strengthening the entire RISC-V ecosystem.

Why This Matters

The momentum around RISC-V continues to build, challenging proprietary architectures and unlocking opportunities across consumer electronics, AI, IoT, and data center applications. S2C’s contributions—through FPGA prototyping, advanced verification methodologies, and ecosystem collaboration—are helping ensure that these innovations reach the market faster and with greater reliability.

As the semiconductor industry navigates an era defined by openness and scalability, companies like S2C are proving essential to making RISC-V not just a promising idea, but a practical reality for next-generation computing.

Source - Semiwiki