Akeana Brings SMT to the Forefront of RISC-V Innovation

Unlocking Efficiency and Performance with Simultaneous Multi-Threading – Akeana’s Vision for the Future of Compute

The story of Simultaneous Multi-Threading (SMT) is one of evolution. For years, it was a specialized tool used mainly in networking workloads and high-end x86 processors. But as the AI era transforms the semiconductor landscape, SMT is emerging as a critical enabler of efficiency and performance across diverse markets.

Akeana, a venture-funded RISC-V startup founded in 2021 by industry veterans, is at the forefront of this shift. In a recent webinar, Graham Wilson and Itai Yarom not only demystified SMT but also showcased Akeana’s leadership in delivering high-performance, SMT-capable IP cores to meet the growing demands of edge AI, data centers, and automotive compute.

From Niche to Necessity

At its core, SMT allows multiple independent threads to run concurrently on the same CPU core. This improves utilization and reduces idle cycles, especially in situations where latency or memory bottlenecks might otherwise stall execution.

The technology is no longer limited to networking. Companies like NVIDIA and Tesla are integrating SMT into their AI-focused SoCs to improve performance-per-watt, manage latency, and handle increasingly complex workloads. The adoption of heterogeneous SoC architectures makes efficient compute resource management essential — and SMT is proving to be a powerful solution.

Akeana’s Multi-Tiered Product Line

Akeana’s approach to SMT is defined by flexibility. Their product lineup includes:

• 100 Series – 32-bit embedded cores for lightweight, real-time applications.

• 1000 Series – Consumer and automotive performance cores.

• 5000 Series – High-performance, out-of-order designs for demanding compute environments.

All these cores can be configured with up to four threads per core, in both in-order and out-of-order microarchitectures, enabling customers to balance power, area, and throughput for specific market requirements.

Beyond Raw Performance

While SMT can deliver impressive performance gains, Akeana emphasizes its role in system-level efficiency. By enabling a single CPU to handle both primary workloads and background system management tasks — such as interrupt handling, accelerator coordination, and housekeeping — SMT reduces the need for multiple CPUs, cutting both bill of materials (BOM) cost and energy consumption.

In automotive contexts, SMT can support dual redundant software instances for safety and fault recovery. In AI training clusters, it can enhance resilience without duplicating silicon.

Security and Reliability as Core Principles

Akeana’s SMT implementations include isolated register files, secure context switching, and telemetry support, making them well-suited for safety-critical and edge environments where workload protection is essential.

Real-World Performance Gains

Akeana’s benchmarks demonstrate the real benefits of SMT:

• 20–30% uplift in Spec scores, even in standard configurations.

• More than 2x improvement in data movement-intensive workloads.

These results are achieved on cores that already deliver strong single-thread performance, underlining the additional efficiency SMT can bring.

Positioned for Industry Leadership

As compute density demands continue to rise and heterogeneous SoCs become the norm, SMT is shifting from a specialized feature to a foundational capability. Akeana stands out as the only independent RISC-V IP vendor offering configurable SMT as licensable soft IP, giving them a clear first-mover advantage.

The market is responding. More than half of Akeana’s customers now request SMT, particularly in automotive, edge inference, and data center applications.

Conclusion
The recent Akeana webinar highlighted not just the technical aspects of SMT but also its growing role in shaping the future of compute. By combining high-performance design, configurability, and robust security, Akeana is helping SMT transition from a niche technology into a cornerstone of modern processor architecture.

Source - Semiwiki