How DTCO is Fast-Tracking the Angstrom Era of Semiconductor Innovation

Design-Technology Co-Optimization (DTCO) may have been around for years, but its role in the development of Angstrom-scale chips has fundamentally transformed. What was once a reactive process has now become a predictive, full-stack strategy enabling next-generation silicon to hit the market faster and with greater efficiency.

A recent collaboration between Synopsys and Intel showcases just how far DTCO has come. Their joint efforts on Intel’s 18A and 18A-P process technologies are not just technical achievements—they represent a new era in how semiconductors are developed, verified, and delivered.

From Back-End Fixes to Front-End Strategy

In its earliest form, DTCO involved aligning design methods with process constraints—usually after most of the process work was complete. It was a back-end function that ensured chips could still meet power, performance, and area (PPA) targets, even as nodes continued to shrink.

However, the reality of modern semiconductor development has changed. As Moore’s Law faces diminishing returns and atomic-scale design introduces new physical limitations, DTCO has evolved into a co-development strategy. Today, DTCO is a critical enabler that influences decisions about transistor architecture, floorplanning, tool optimization, and IP integration from the very beginning.

Intel 18A and the Power of Early Silicon

This evolution was on full display during the 2025 Intel Foundry Direct Connect event. On stage, Synopsys CEO Sassine Ghazi presented a test chip built on Intel’s 18A process—a chip that had been manufactured nearly a year ahead of schedule.

That chip wasn’t just a marketing prop. It was proof that early and continuous DTCO collaboration, spanning everything from process definition to design tool enablement, can produce functional silicon well before traditional timelines.

This would have been unimaginable in previous generations of semiconductor design. Only through tight coordination and full-stack optimization between Synopsys and Intel was this kind of early readiness made possible.

DTCO in Practice: RibbonFET and PowerVia

The 18A platform introduced major innovations in transistor architecture and power delivery. Synopsys worked hand-in-hand with Intel to align its EDA tools with these changes—most notably RibbonFET and PowerVia.

RibbonFET, Intel’s next-generation gate-all-around transistor architecture, introduced new challenges in timing closure and design convergence. Synopsys integrated RibbonFET-awareness into its place-and-route tools, enabling design teams to reduce closure cycles and boost productivity.

At the same time, PowerVia—Intel’s backside power delivery system—required new strategies for IR drop management and floorplan restructuring. DTCO enabled early modeling and integration of PowerVia into Synopsys’ floorplanning tools, ultimately delivering improved power efficiency across the board.

These are not just incremental gains. They are the result of deeply integrated, predictive co-development that starts well before any silicon is built.

Introducing PICO: The Next Phase of Co-Optimization

To manage this expanded scope, Synopsys introduced a methodology called PICO, which stands for Process-IP-Co-Optimization. PICO represents a structured, pre-silicon flow that brings together:

• Process assumptions based on TCAD simulations

• Standard cell and library development

• IP architecture with process-performance trade-offs

• CAD and EDA tool readiness

• 3DIC and packaging integration

This full-stack framework ensures that every aspect of the chip—process, IP, and tools—is developed in tandem, under real-world constraints. PICO enables early validation, reduces late-stage surprises, and accelerates time-to-market.

Enabling a Faster, Lower-Risk Path to Market

One of the most significant benefits of DTCO and PICO is the creation of what Synopsys calls the "enablement readiness cycle." This process ensures that validated design flows, certified IP, and foundry-aligned tools are ready in sync with technology ramp-ups.

For Intel’s 18A node, Synopsys had its IP libraries and toolchain prepared before first silicon. This readiness reduces risk, accelerates product schedules, and ensures that customers can confidently design on a new process node without delays or compatibility concerns.

The Strategic Value of DTCO in the Angstrom Era

Modern DTCO is no longer a niche process optimization technique—it is a strategic capability. As the semiconductor industry moves toward angstrom-level nodes, the complexity of design and process integration only increases. Foundries, EDA vendors, and IP providers must work together from the earliest stages to succeed.

Synopsys and Intel’s work on the 18A platform demonstrates what is possible when this collaboration is taken seriously. Through DTCO and PICO, they have not only delivered early silicon but also set a blueprint for the future of chip design in the Angstrom era.

DTCO is now a competitive edge. It determines which companies bring innovations to market first, with the best performance and the lowest risk. As design complexity continues to scale, those who embrace co-optimization across the stack will define the next generation of semiconductors.

Conclusion

The industry is entering a new era of semiconductor design—one that demands collaboration, integration, and front-loaded innovation. DTCO, when treated as a strategic discipline rather than a downstream fix, has the power to transform timelines, reduce risk, and unlock new levels of performance.

With frameworks like PICO and partnerships like Synopsys and Intel, the Angstrom era is not just a vision—it’s already underway.

Source - Semiwiki